RegViz: Visualize INT

Espressif Systems /ESP32-S3 /MCPWM0 /INT_ENA

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Interpret as INT_ENA

Description

Interrupt enable bits

Fields

TIMER0_STOP_INT_ENA	The enable bit for the interrupt triggered when the timer 0 stops.
TIMER1_STOP_INT_ENA	The enable bit for the interrupt triggered when the timer 1 stops.
TIMER2_STOP_INT_ENA	The enable bit for the interrupt triggered when the timer 2 stops.
TIMER0_TEZ_INT_ENA	The enable bit for the interrupt triggered by a PWM timer 0 TEZ event.
TIMER1_TEZ_INT_ENA	The enable bit for the interrupt triggered by a PWM timer 1 TEZ event.
TIMER2_TEZ_INT_ENA	The enable bit for the interrupt triggered by a PWM timer 2 TEZ event.
TIMER0_TEP_INT_ENA	The enable bit for the interrupt triggered by a PWM timer 0 TEP event.
TIMER1_TEP_INT_ENA	The enable bit for the interrupt triggered by a PWM timer 1 TEP event.
TIMER2_TEP_INT_ENA	The enable bit for the interrupt triggered by a PWM timer 2 TEP event.
FAULT0_INT_ENA	The enable bit for the interrupt triggered when event_f0 starts.
FAULT1_INT_ENA	The enable bit for the interrupt triggered when event_f1 starts.
FAULT2_INT_ENA	The enable bit for the interrupt triggered when event_f2 starts.
FAULT0_CLR_INT_ENA	The enable bit for the interrupt triggered when event_f0 ends.
FAULT1_CLR_INT_ENA	The enable bit for the interrupt triggered when event_f1 ends.
FAULT2_CLR_INT_ENA	The enable bit for the interrupt triggered when event_f2 ends.
CMPR0_TEA_INT_ENA	The enable bit for the interrupt triggered by a PWM operator 0 TEA event
CMPR1_TEA_INT_ENA	The enable bit for the interrupt triggered by a PWM operator 1 TEA event
CMPR2_TEA_INT_ENA	The enable bit for the interrupt triggered by a PWM operator 2 TEA event
CMPR0_TEB_INT_ENA	The enable bit for the interrupt triggered by a PWM operator 0 TEB event
CMPR1_TEB_INT_ENA	The enable bit for the interrupt triggered by a PWM operator 1 TEB event
CMPR2_TEB_INT_ENA	The enable bit for the interrupt triggered by a PWM operator 2 TEB event
TZ0_CBC_INT_ENA	The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0.
TZ1_CBC_INT_ENA	The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1.
TZ2_CBC_INT_ENA	The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2.
TZ0_OST_INT_ENA	The enable bit for the interrupt triggered by a one-shot mode action on PWM0.
TZ1_OST_INT_ENA	The enable bit for the interrupt triggered by a one-shot mode action on PWM1.
TZ2_OST_INT_ENA	The enable bit for the interrupt triggered by a one-shot mode action on PWM2.
CAP0_INT_ENA	The enable bit for the interrupt triggered by capture on channel 0.
CAP1_INT_ENA	The enable bit for the interrupt triggered by capture on channel 1.
CAP2_INT_ENA	The enable bit for the interrupt triggered by capture on channel 2.

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